Abstract: Advances in packaging technologies, combined with reduced bump pitches are rapidly enabling the disaggregation of large SoCs into chiplet based System in Package (SiP) solutions. Development and adoption of the UCIe standard has paved the way for power efficient, low latency, high bandwidth D2D link designs that are crucial to enable the disaggregation of high-performance systems. SerDes transceivers need to adopt advanced circuit techniques to meet the challenging performance targets of these D2D links. This talk will explore the architectural challenges of both...