In our research, we investigate permittivity-based sensing and imaging techniques at mmWave and sub-THz frequency range for real-time in-vitro monitoring of biological samples at the single cell and tissue levels.
My work is on designing bulk cmos power amplifiers that can operate across the entirety of the Ka (26.5- >40GHz) frequency band. This is done by the use of broadband, transmission line type of passive structures.
In an FMCW radar system, Tx and Rx must operate concurrently. Thus the chirp signal can leak from multiple places of the Tx into the Rx chain, often at significantly higher power than the reflection from the actual targets, causing saturation in the various stages of Rx and reducing dynamic range of the receiver. In our 140GHz FMCW radar chip, we proposed and implemented a method to mitigate the ...
Coherent Transceivers for Intra data center Co-Packaged Optical Links
As the bandwidth density requirement of intra-data center links keep on increasing, optical interconnects play a significantly important roles compared to the conventional electrical interconnects. Co-packaged optics, in contrary to the standard pluggable optics solutions, is capable of bringing a revolution in bandwidth density of optical interconnects due to the reduced length of electrical channels which increases the baud rate of data transfer. On the top of that, making the best use of...
High Efficiency Transmitters for 5G and 6G communication systems
High Efficiency transmitters are critical for modern communication systems. The focus of this research is to design efficient TX elements while providing linear response in order to get high data rates.
We are investigating the usage of parametric generators for stimulus generation for fuzzing hardware.
We leverage the highly controllable and instrumentable nature of parametric generators to apply machine learning techniques to guide the mutation and selection algorithms in a fuzzing loop. We implement a RISC-V instruction generator as a parameteric generator and apply fuzzing to produce programs that target different microarchitectural metrics or coverpoints.
Vikram Jain received his M.Sc degree in Embedded Electronics Systems Design (EESD) from Chalmers University of Technology, Sweden, in 2018, and his PhD degree in Electrical Engineering from KU Leuven, Belgium, in 2023. His PhD research was in implementation of energy efficient digital acceleration and RISC-V processors for machine learning applications at the edge. He was also a visiting researcher at the IIS lab in ETH Zurich working on implementation of networks-on-chip. He is currently a postdoctoral researcher at SpeciaLIzed Computing Ecosystems (SLICE) lab and Berkeley Wireless...
My research focuses on SoC integration and hardware-software co-design opportunities in multi-accelerator systems, spanning from hardware architecture and SoC design to system software and schedulers.
