Vighnesh Iyer

Parametric Fuzzing for Hardware Verification

We are investigating the usage of parametric generators for stimulus generation for fuzzing hardware.

We leverage the highly controllable and instrumentable nature of parametric generators to apply
machine learning techniques to guide the mutation and selection algorithms in a fuzzing loop. We
implement a RISC-V instruction generator as a parameteric generator and apply fuzzing to produce
programs that target different microarchitectural metrics or coverpoints.