Researcher

Discrete Envelope Tracking for Wideband mm-Wave Power Amplifiers

Envelope tracking (ET) is in wide use to improve the efficiencies of power amplifiers (PA) which increases
battery life of multiband wireless communication systems. Although most supply modulators (SM) adopt
a hybrid topology which is composed of a high-efficiency switching converter and wide-bandwidth linear
amplifier, it has reached their intrinsic limitation in terms of channel bandwidth. This is due to the new
specifications of the uplink channel bandwidth of 5G FR2 up to 400MHz for...

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Carla Benato

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Savit Bhat

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Rohit Braganza

Transmission Line Transformers for Broadband K/Ka Power Amplifiers in Bulk CMOS

My work is on designing bulk cmos power amplifiers that can operate across the entirety of the Ka (26.5-
>40GHz) frequency band. This is done by the use of broadband, transmission line type of passive
structures.

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Yikuan Chen

Towards Wideband Linear RF Transmitters for Millimeter-Wave Arrays

In an FMCW radar system, Tx and Rx must operate concurrently. Thus the chirp signal can leak from
multiple places of the Tx into the Rx chain, often at significantly higher power than the reflection from
the actual targets, causing saturation in the various stages of Rx and reducing dynamic range of the
receiver. In our 140GHz FMCW radar chip, we proposed and implemented a method to mitigate the
...

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Yufeng Chi

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Junsun Choi

RPC Integration on hyperscale accelerators

Integrating the RPC layer to an SoC that consists of hyperscale accelerators, optimizing the software-
level scheduling of workloads

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Junsun Choi

Electrical Engineering and Computer Sciences

Junsun is a 5th-year PhD student advised by Prof. Bora Nikolic and Prof. Sophia Shao. He received his bachelor's degree in Electrical and Computer Engineering at Seoul National University in 2021. His past projects include data (de)compression accelerator for hyperscale systems, hyperscale SoC tapeout, and remote procedure call (RPC) accelerator scheduling for hyperscale workloads. His current research focus is building a scalable area-performance model for designing the next-generation datacenter across chip, package, and network levels.