Open Source Memory Systems
Although DRAM is pervasive in almost all modern computing systems, academic research thus far has
been limited to high-level simulations (e.g., DRAMSim). While these simulators can serve well for
general architectural explorations, they often fail to capture implementation-based latencies (i.e., PHY)
and negotiation of commercial interfaces (DFI). Additionally, microarchitectural explorations and
security research would require physical implementations for realistic investigation. A critical example is
the ongoing RowHammer security exploit that utilizes the electrical failure of a memory row to cause
significant data alterations. Coupled with the fact that the lack of DRAM memory system
implementations continues to place a significant limit on academic chip designs, developing such a
memory system has proven to be important. This project seeks to address this defecit by developing an
LPDDR4X compliant memory controller and PHY.
Expected Graduation Date:
May, 2027