A Generated 4 GS/s 124.6 mW 8× Time-Interleaved SAR-VCO ADC with 9.1 ENOB

This work presents an eight-way time-interleaved SAR-VCO ADC implemented in the Intel 16 process that operates at 4GS/s with 9.1 ENOB resolution. The sub-ADC design combines SAR and time-domain data conversion and uses a ring amplifier for the interstage residue amplification. The ADC achieves SNDR and SFDR of 56.5 dB and 72.9 dB with a Nyquist frequency input. The ADC core occupies 0.36 mm2 and consumes 124.6 mW, yielding the FoM W and the FoMS of 57.1fJ/ conv.-step and 158.4 dB. The implemented ADC is an instance produced by a highly parameterized circuit generator that enables rapid design-space exploration through automated circuit generation.