Dhiraj:Dhiraj is CEO and Founder of Silitronics. He has 10 years of experience in package design and assembly. Then, another 10 years in sales where he grew his accounts from $20M/year to $200M/year. At Silitronics, he defined the strategy to focus on complicated process development, flip chip build up substrate fabrication and silicon photonics assembly with fully automated active alignment. He held engineering and sales roles at large companies (Lucent, JDSU, ASE) and startups (Onix, SLM, MicroDisplay). He has been grewing Silitronics every year since it was founded. He has a BS in Mech Eng from U of Ottawa, Canda, while ranking first in his class. In his spare time, he plays golf, cricket and soccer, hikes and trades options in stock market as well as follows 49ers and Warriors.
Suresh: Suresh is CTO of System Engineering and Package Design. He has 25+ years of experience. His experience includes System Technology Co-Optimization (STCO) spanning chip, package, PCB, and systems. Recently, he has been involved in several advanced packaging projects for 3DIC HI and proposed an architecture for a plug-and-play chiplet platform. He also developed a methodology for early architectural analysis, STCO, and construction of multi-chiplet packages. He held senior engineering roles at large companies (Xilinx/AMD, Ericsson, Cadence, Applied Micro) and startups (CSwitch, Tabula, Apex Semi). He has successfully delivered complex packages for multiple generations of HPC SoCs with responsibilities including chip, package, PCB co-design, package architecture, Signal, and Power Integrity as well as DFM and DFA. He has 12 patents. He has an MS and PhD from USC and an MBA from the Leavey School of Business.
Talk Title: Package Design and Chiplet’s
Abstract: In this talk, we will outline a chiplet based Reconfigurable Open Compute Accelerator Module (ROAM) platform. In Opencompute Accelerator Infrastructure (OAI), reuse, scalability, and modularity of hardware is defined up until the OAM. This new platform leverages existing OAI infrastructure and extends this into advanced packaging and chiplets. We will outline the specifics of a System in Package (SiP). The SiP will also have standard footprints to house up to 8 domain specific accelerators (DSA) chiplets, IO chiplets, and hub/bridge/switch chiplets. Standardization of the chiplet footprints enables a highly modular, scalable , ROAM platform. This platform has the potential to usher in the era of Plug and Plug Chiplets (PnPC). We will also discuss how this platform can be extended to included Silicon Photonics and CXL based memory.
Title Talk:Silicon Photonics and Automated Active Alignment
Abstract:In this talk, we will outline the challenges in assembly of Silicon Photonics Assembly among a FAU to PIC to SOA. Then, Silitronics will provide a approaches to minimize the risk with a proven DFM and DFA plan while using Fully Automated Active Alignment System.
