Talk Title: From Tokens to Tapeout: LLM Agents Tackling the Hard Problems of Modern Chip Design
Talk Abstract: Chip design sits at the intersection of two of the hardest problems in engineering: the combinatorial complexity of modern semiconductor systems and the depth of expert knowledge required to close them. This talk explores how LLM-powered agentic systems are beginning to change that reality — not as curiosities, but as production tools reshaping how engineers work across RTL generation, analog signoff, physical design, and verification. We examine what works, what breaks, and what remains stubbornly unsolved — from representing design knowledge in forms agents can reason over, to evaluating correctness without ground truth, to sustaining coherent intent across flows that span days. The goal is not to present a finished system, but to map the frontier and invite the next generation of researchers to help push it.
Raghav Vasappanavara is a Senior Design Engineering Architect at Cadence's Silicon Solutions Group, where he leads Applied AI and systems innovation for end-to-end Silicon IPs, chiplets, and custom silicon product development. With close to two decades of experience in technical leadership roles architecting tools, flows, and methodologies (TFM) across Intel, Qualcomm, and AMD, he brings a practitioner's understanding of the full silicon lifecycle to driving AI-powered transformation in how silicon is designed and delivered. He is a graduate of UCSD in applied data science.