Researcher

Vighnesh Iyer

Parametric Fuzzing for Hardware Verification

We are investigating the usage of parametric generators for stimulus generation for fuzzing hardware.

We leverage the highly controllable and instrumentable nature of parametric generators to apply
machine learning techniques to guide the mutation and selection algorithms in a fuzzing loop. We
implement a RISC-V instruction generator as a parameteric generator and apply fuzzing to produce
programs that target different microarchitectural metrics or coverpoints.

Camille Jubert

Averal Kandala

BASE: Bio-implantable Arrayed Sensing Environment

The Bio-implantable Arrayed Sensing Environment (BASE) seeks to address a fundamental problem in critical disease tracking: the lack of quick and actionable diagnostic feedback on applied therapies. It is composed of an implant ASIC, BASE-Hub, and a wireless power and data transfer setup, BASE-Link. Acting as an implantable hub deep within the body for sensor control, persistent data storage, and wireless power and data transfer via inductive coupling, BASE-Hub enables unprecedented long-term, asynchronous diagnostic...

Josh (Minwoo) Kang

Novel Design Methodologies for Digital Design: Machine Learning and Agile Methods

Research on applications of machine learning (ML) that enable automated and/or improved digital
design processes. Approaches include geometric learning and utilization of large language models
(LLMs).

Nazem Khairallah

Awani Khodkumbhe

Digital I/Q Sharing mm-wave Transmitters for WiFi

While some attempts have been made to realize digital PAs at mm-wave bands, most demonstrations to date have produced relatively low resolution transmitters and are more suitable for simple modulation schemes. Here we propose a new architecture which can generate 64-QAM using basic I/Q unit elements. For 16-QAM, only 3 are needed, while 64-QAM requires 7 units. Each unit is driven by a constant power signal from the VCO. A series of injection locked VCOs can be used to drive sufficient power without incurring passive...

Hansong Kim

Kunmo Kim

Advanced Non-Linear ISI Equalization for ADC-Based SerDes

Developed both NRZ/PAM-4 non-linear equalizers outperforming conventional FFE-DFE performance.

Seah Kim

Scalable ML accelerator SoC integration

My research focuses on SoC integration and hardware-software co-design opportunities in multi-accelerator systems, spanning from hardware architecture and SoC design to system software and schedulers.

Sophia Koh